MIPI DSI PCB Layout Notes

MIPI DSI PCB layout requires you to follow the same routing and layout rules that any other differential pair type interface would demand. I could not find all the information required for routing MIPI DSI traces in one place, so I thought I’d put together an article that contains a summary of everything that you need to keep in mind while laying out a PCB with MIPI DSI traces on it.
DSI interface can have a variable number of data lanes. A higher lane count option is preferable if you can have it because the data rate per lane decreases (given the same resolution and frame rate), making the system more tolerable to layout errors or PCB stackup effects.
Listed below is information that can come in handy when laying out your next DSI board.
A typical MIPI DSI host to display connection looks like this:
MIPI DSI interface and differential pairs
Differential Pairs in MIPI DSI Interface (Source: TI SPRACP4)

1. The Usual High Speed PCB Layout Rules

You still need to follow all the rules that would apply to digital logic speeds reaching over 100 MHz. Remember, 100+ MHz digital logic carries 1GHz components too, because square waves contain higher order harmonics.

Therefore, the following rules will always apply:

  • Do not run MIPI DSI traces across gaps in ground plane.
  • No split ground plane anywhere that interrupts the return current path under MIPI DSI traces.
  • Avoid having vias between a differential pair if you can.
  • Avoid using vias to carry MIPI DSI signals to other layers if possible. Using vias should be a last choice.
  • The maximum clock that you will see on a MIPI DSI interface is 500 MHz, therefore it is important to shield these lines from other pairs and other electronics nearby that can be affected, such as WiFi or BT chipsets or antennas.

2. Controlled Impedance Traces

Single ended impedance: 50 ohms (tolerance: +/- 15%)
Differential impedance: 90 ohms (tolerance: +/- 15%)

On a typical 1.6mm FR4 PCB with 7628 type stackup (4 layers), the above specifications usually result in 4.5 mil wide traces with about 6 mils of gap between the traces. This can vary, make sure you calculate it using an online impedance calculator or similar tool.

3. Reference Plane

MIPI DSI bus reference plane can be GROUND or POWER.

This means that you can use vias to route DSI lines on the bottom side of a 4-layer board without worrying about signal integrity problems.

NOTE that you need to add 10nF capacitors on both sides of the lines between POWER and GROUND for handling return currents on change of reference plane.

4. Length Matching and Constraints

MIPI DSI interface provides for a synchronous clock to which all data pairs are referenced. Therefore, the data lanes must be matches to the clock pair.
Maximum length difference within a differential pair:
0.15 mm or 5 mils
Maximum length difference between differential pairs:
1.5 mm or 50 mils
Maximum recommended length of the clock differential pair:
200 mm or 7800 mils
Stubs on differential traces:
None allowed
Change Log
  • Initial Release: 23 May 2021

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