SDRAM Byte and Bit Swapping – Can you do it?

by Pratik (A PCBArtist)

SDRAM pin swapping is a term used to refer to a variety of techniques used to simplify PCB design where an MCU and SDRAM are involved. SDRAM swapping rules can be used in a number of ways to avoid using several vias on a signal that is a part of the high speed memory bus. The primary types of pin swapping that you will find to be in use with SDR and DDR SDRAM chips are

  • Data lane swapping or byte swapping
  • Data line swapping or bit swapping
  • Address line swapping
Knowing the rules for bit and byte swapping can come in handy when using moderately high speed MCUs with ARM Cortex M- series cores that have external memory controller interfaces. Using these rules can make SDRAM PCB layout much easier.
NOTE: In the rest of this article, “DDR” refers primarily to DDR3 or DDR3L as it is the most common type being used with ~1 GHz systems.

Swapping in SDR SDRAM vs DDR SDRAM

It is important to distinguish between regular SDR SDRAM and DDR memories.

SDR SDRAM are usually used with slow systems such as embedded systems running at a frequency slower than 300 MHz. The important identifier for SDR SDRAM chips is the lack of a differential clock line.
DDR memories, as the name suggests, use double data rate. The clock and strobe timings are extremely important to achieve high data rates without error.
The main different in terms of swapping in SDR and DDR memories is the fact that DDR memories have read and write leveling, whereas SDR memories do not need that.

Types of Swapping Usable with SDRAM

I listed the types of swapping options that are commonly used with PCB design involving SDRAM chips. Here is a closer look at why you can or cannot use a certain swap option.

Lane or Byte Swapping

Yes, you can do this with an SDR SDRAM chip. However, make sure that you have other related control pins swapped as well, for example the data lane mask pins for the two lanes must be swapped too.
For example, if you have a memory chip with 16-bit data bus, the data bus can be divided into bytes:

Byte 0:
DQ[0] to DQ[7]
Byte 1: DQ[8] to DQ[15]

The byte 0 is sometimes called the lower data byte and marked as LD, while the upper byte is called the UD.

You can connect DQ[8] to DQ[15] of the MCU to the SDRAM memory chip’s DQ[0] to DQ[7] too without issues. Howevery, make sure you have the LDQM, UDQM and other such byte-specific signals swapped too.

Data Line or Bit Swapping

Yes, you can do this with an SDR SDRAM chip.

There are no restrictions on swapping of data lines inside a certain data byte. This swapping rule can be used in addition to the rule above.

Note that you cannot swap data lines between bytes, i.e. you can swap DQ[3] and DQ[6]. But you cannot swap DQ[2] with DQ[13].

The reason for this restriction should be obvious to you. The mask signals, LDQM and UDQM control a certain byte and therefore you cannot swap out lines outside a certain byte because the mask logic will fail.

NOTE: You should still double-check with your SDRAM datasheet to make sure that it has no special functions associated with a certain data bit. For example, DDR memories do not allow DQ[0] and DQ[8] to be swapped with any other bits because they are used for read/write leveling function.

Address Line Swapping

No, cannot do this with an SDR SDRAM chip.

SDRAM memories read configuration information via the address lines. Therefore, swapping the address lines can set the whole chip up incorrectly resulting in access errors.
sdram address lines mode register setting
Address Lines and Mode Register Settings - IS42S16400J Datasheet

Now, you can compensate for this swap in firmware when you set the SDRAM memory up, but that still does not solve the problem.

Swapping of address lines will not be a cause of trouble if you only perform word- or byte- level access, i.e. if you only feed an address and read the data word available on that address.
However, a problem shows up when using burst mode read and write operations. Those operations auto increment the address pointer and will probably throw the pointer all over the address space if your address bus lines are swapped. Not having a proper page increment operation will mean out-of-sequence data blocks being read.
Not just this, a bit of the address bus, for example the address line A10 may be used as a dedicated line for auto precharge by the memory controller. Swapping it out can cause problems as well.

Now you know the basics of what works and what to look for when it comes to interfacing between an MCU or FPGA and SDRAM memory chips.

It is ALWAYS recommended to consult the MCU or FPGA memory controller datasheet and the SDRAM chip datasheet before you finalize any hardware design!

Change Log
  • Initial Release: 23 May 2021

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