I2C Register Description

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Summary: This page describes the I2C registers available on the PCBA-DBM-r3 module.

The PCBA-DBM-r3 module interacts with the host MCU via a series a I2C registers.
These registers are documented in this article.

VERSION – Register 0

Address	Default Value	Type
0x00	0x31	R/O

➤ Bit [7:4] – HW Version
➤ Bit [3:0] – FW Version
All PCBA-DBM-r3 modules will have VERSION = 0x31
This register can be used by the host MCU to identify which sensor model is connected.

UNIQUE_ID – Registers 1, 2, 3, 4

Address	Default Value	Type
0x01 – 0x04	32-bit Unique ID	R/O

➤ Bit [31:0] – Unique Device ID
Every PCB Artists sensor has a random 32-bit unique ID.

SCRATCH – Register 5

Address	Default Value	Type
0x05	–	R/W

➤ Bit [7:0] – Scratchpad Register
The host MCU may write and read any value from this register at any time.
Writing and reading back values from this register may be useful for I2C communication testing and debugging.

CONTROL – Register 6

Address	Default Value	Type
0x06	0x02	R/W

➤ Bit [7:5] – Reserved
Do not write 1 to these bits
➤ Bit [4] – Interrupt Type
Set to enable minimum/maximum level interrupts.
→ If 1, THR_MIN and THR_MAX registers are used as threshold values. When a decibel reading goes outside the range set by THR_MIN and THR_MAX, interrupt pin is activated.
→ If 0, INT pin goes low when 90 of the 100 DB_HISTORY registers are filled with readings.
➤ Bit [3] – Interrupt Enable
Set to enable the interrupt pin operation. INT pin goes low to indicate a pending interrupt.
A pending interrupt must be cleared by writing to the RESET register.
➤ Bit [2:1] – Filter Selection
Select a frequency weighting filter to apply to decibel reading
→ 00 – Z-weighting (No weights)
→ 01 – A-weighting (default)
→ 10 – C-weighting
→ 11 – Reserved
➤ Bit [0] – Power Down
Set this bit to power down the decibel sensor. Writing a 0 does nothing.
NOTE: To power up the module, the host must set bit[3] of RESET register to cause a module reset.
Failing to do so can put the module in an unknown state. After wake-up and reset, the module settings are restored to their power-up default state and application can use the module as usual.

TAVG_HIGH – Register 7

Address	Default Value	Type
0x07	0x03	R/W

➤ Bit [7:0] – Tavg_high
Weighting time (high byte) in milliseconds applied for calculating decibel value. This register, and TAVG_LOW register together form a 16-bit Tavg value.
→ Set [Tavg_high:Tavg_low] = 1,000 for slow mode intensity measurement.
→ Set [Tavg_high:Tavg_low] = 125 for fast mode intensity measurement.
NOTE: A range of 10 to 10,000 is supported for 16-bit Tavg value.

TAVG_LOW – Register 8

Address	Default Value	Type
0x08	0xE8	R/W

➤ Bit [7:0] – Tavg_low
Weighting time (high byte) in milliseconds applied for calculating decibel value. This register, and TAVG_HIGH register together form a 16-bit Tavg value.
NOTE: Writing to Tavg_low causes the combined value of Tavg_high:Tavg_low to take effect. Therefore, Tavg_high must be written first.
As Tavg is a 16-bit value, Tavg = 256*TAVG_HIGH + TAVG_LOW
NOTE: A range of 10 to 10,000 is supported for 16-bit Tavg value.

RESET – Register 9

Address	Default Value	Type
0x09	0x00	W/O

➤ Bit [7:4] – Reserved
Do not write 1 to these bits
➤ Bit [3] – System Reset
Set this bit to trigger a system reset. All module registers are restored to their default values as mentioned in this register map. This bit is automatically cleared.
NOTE: This bit must be set to wake up the device from sleep mode.
➤ Bit [2] – Reset History
Set this bit to clear the most recent 100 decibel values stored in history registers. This bit is self-clearing.
NOTE: When INT mode is set to indicate a full buffer, user must set this bit to clear history first, and then reset the interrupt by setting bit 0.
➤ Bit [1] – Reset Min/Max
Set this bit to clear the maximum and minimum noise level values stored in MAX and MIN registers. This bit is self-clearing.
➤ Bit [0] – Reset Interrupt
Set this bit to clear interrupt signal and set INT pin to high-Z. This bit is self-clearing.
NOTE: If INT signal is set to interrupt on a full buffer, the HISTORY buffers must be cleared before resetting the INT signal using this bit.

DECIBEL – Register 10

Address	Default Value	Type
0x0A	0x00	R/O

➤ Bit [7:0] – Sound Level Reading in dB SPL
Latest sound intensity value in decibels, weighted over the last Tavg time period, frequency-weighted as per weighting set via CONTROL register.
NOTE: The decibel reading is only valid after about 1 second of module power-up.

MIN – Register 11

Address	Default Value	Type
0x0B	undefined	R/O

➤ Bit [7:0] – Minimum Observed Decibel Reading
Minimum value of decibel reading captured since power-up or manual reset of MIN/MAX registers.

MAX – Register 12

Address	Default Value	Type
0x0C	undefined	R/O

➤ Bit [7:0] – Maximum Observed Decibel Reading
Maximum value of decibel reading captured since power-up or manual reset of MIN/MAX registers.

THR_MIN – Register 13

Address	Default Value	Type
0x0D	45’d	R/W

➤ Bit [7:0] – Lower Decibel Threshold
Minimum decibel value (threshold) under which interrupt should be asserted.

THR_MAX – Register 14

Address	Default Value	Type
0x0E	85’d	R/W

➤ Bit [7:0] – Upper Decibel Threshold
Maximum decibel value (threshold) above which interrupt should be asserted.

DBHISTORY – Registers 20 to 119

Address	Default Value	Type
0x14 (DBHISTORY_0)	0x00	R/O
•••	•••	•••
0x77 (DBHISTORY_99)	0x00	R/O

➤ Register 20 (0x14)to Register 119 (0x77) – History values for the last 100 Tavg time periods
Past decibel values arranged in a queue, captured every “Tavg” milliseconds.
DBHISTORY_99 contains the oldest data. New decibel readings from the DECIBEL registers are inserted into DBHISTORY_0 every “Tavg” interval and data is shifted back as new data is available.

Revision History

➤ September 2, 2025
– Initial release